In a DRAM array, oxide spacers at the edges of field-effect transistor gates generally serve a two-fold purpose. Firstly, they are used to offset source and drain dopant implants from the gate, so that subsequent high-temperature drive steps will not cause the source and drain implants to diffuse together. In a transistor having both lightly and heavily doped regions within the junctions on both sides of the gate (commonly referred to as a lightly-doped drain or LDD transistor) a primary spacer is utilized to offset the low-dosage implant (phosphorus is generally used for the low-dosage implant in an N-channel device) from the gate, while a secondary spacer is utilized to offset the high-dosage implant (typically arsenic in an N-channel device) from the gate and low-dosage implant. Secondly, spacers are also used to insulate the digit line from the transistor gate. Since FET gates in a DRAM array column are interconnected by a word line (which is generally formed from the same layer of material as the gates), spacers are formed simultaneously along the edges of word lines and transistor gates.
A spacer formation and source/drain doping process is depicted in FIGS. 1 through 4. This process is identical to the one used by Micron Technology, Inc. for the fabrication of its proprietary 4-megabit DRAMs.
Referring now to FIG. 1, a pair of N-channel field-effect transistor gates 11 within a DRAM array have been created on a lightly-doped, p-type monocrystalline silicon substrate 12 by etching a triple-layer sandwich of polysilicon 13, tungsten silicide 14, and silicon dioxide 15. Gates 11 are insulated from substrate 12 by a gate oxide layer 16. Following the blanket deposition and subsequent high-temperature densification of a first conformal tetraethylorthosilicate (TEOS) oxide layer 17, the source/drain regions 18 receive a low-dosage implanting with phosphorus.
Referring now to FIG. 2, the array receives a blanket deposition of a second conformal TEOS oxide layer 21.
Referring now to FIG. 3, the array is subjected to an anisotropic etch which consumes portions of both first TEOS layer 17 and second TEOS layer 21, leaving spacers 31. It will be noted that the anisotropic etch has also reduced the thickness of silicon dioxide layer 15. Subsequent to the anisotropic etch, source/drain regions 18 receive a high-dosage implanting with arsenic.
Referring now to FIG. 4, either a wet isotropic etch or a vapor isotropic etch is employed to widen region 41 where the future bit line will make contact with substrate 12. This etch step consumes the remainder of second TEOS layer 21 and reduces the thickness of the remaining portion of TEOS layer 17. The remaining spacer 42 has a nearly vertical wall portion 43 and a nearly horizontal foot portion 44. In addition some undercutting has taken place at intersection region 45 where vertical wall portion 43 and horizontal foot portion 44 intersect.
During the etch of subsequently deposited polysilicon layers, polysilicon stringers sometimes remain in the undercut intersection region 45. FIG. 5 shows the cross-sectional outline of stringers 51 which have remained in intersection region 45. Since stringers usually run for at least a portion of the length of a word line, they have the potential for shorting the bit line of one row to the bit line of one or more other rows, making the region of the array so affected non-functional. Another disadvantage of the nearly vertical spacer walls is the difficulty of obtaining acceptable step coverage for the future bit line connection. Generally, the steeper the spacer wall, the worse the step coverage.
What is needed is a process for creating a spacer having a new configuration characterized by walls that are less steep, no undercut region, and still thin in order to maximize the size of the bit line contact region on the substrate.